Switched-capacitor circuits typically include switches, along with amplifiers, in arrangements configured to implement specific input-to-output transfer functions. For example, switched-capacitor circuits can be used to implement gain stages, filters, D/A converters, and many other types of circuits. The switches of switched-capacitor circuits are selectively switched on and off by clock signals to realize the transfer functions.
FIG. 1 depicts an exemplary switch 20 that could be used in a switched-capacitor circuit. The switch 20 includes a first terminal associated with a first voltage V1, a second terminal associated with a second voltage V2, and a switching terminal configured to receive a clock signal VCLK. In an enabled state, the switch 20 is closed and connects the first terminal to the second terminal. In a disabled state, the switch 20 is open and the first and second terminals are isolated from each other. The switch 20 is enabled and disabled according to the clock signal VCLK received at the switching terminal.
Switches suitable for use in switched-capacitor circuits, such as the switch 20 depicted in FIG. 1, can be implemented by arrangements of transistors operated in a switching mode. FIG. 2 shows an exemplary transistor implementation 22 of the switch 20 depicted in FIG. 1. The exemplary transistor implementation 22 includes an NMOS transistor N1 and a PMOS transistor P1, arranged in parallel, with the source of the NMOS transistor N1 and the drain of the PMOS transistor P1 connected together, the drain of the NMOS transistor N1 and the source of the PMOS transistor P1 connected together, and gates of the NMOS and PMOS transistors N1, P1 configured to receive the clock signal VCLK its inverse VCLK, respectively. When the clock signal VCLK has a logic-high value, the switch embodiment 22 of FIG. 2 is enabled, and both the NMOS and PMOS transistors N1, P1 are turned on. When the clock signal VCLK has a logic-low value, the switch 22 is disabled, and both the NMOS and PMOS transistors N1, P1 are turned off.
One problem, however, with the transistor implementation 22 of FIG. 2, and with other transistor implementations of the switch 20, is that they typically implement non-ideal switches. Generally speaking, an ideal switch presents zero impedance between its first and second terminals when enabled, and infinite impedance between these terminals when disabled. However, the transistor implementation 22 of FIG. 2, and also other transistor implementations, typically presents, among other non-ideal characteristics, a non-zero resistance between the first and second terminals when enabled. This is due to, e.g., a non-zero impedance of the conduction channel formed between the sources and drains of the NMOS and PMOS transistors N1, P1 of FIG. 2 when turned on.
Non-ideal switches can in turn impact the performance of switched-capacitor circuits containing such switches. A switched-capacitor circuit, which includes the transistor switch embodiment 22 of FIG. 2, or other non-ideal switch embodiments, in a signal path, may suffer from adverse effects of the non-zero impedance in the enabled state. For example, this non-zero impedance may adversely affect a frequency response of the switched-capacitor circuit.